STS3DNE60L n - channel 60v - 0.065 w - 3a so-8 stripfet ? power mosfet preliminary data n typical r ds(on) = 0.065 w n standard outline for easy automated surface mount assembly n low threshold drive description this power mosfet is the latest development of stmicroelectronics unique " single feature size ? " strip-based process. the resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics and less critical alignment steps therefore a remarkable manufacturing reproducibility. applications n dc motor drive n dc-dc converters n battery managment in nomadic equipment n power management in portable/desktop pc s ? internal schematic diagram may 1999 so-8 absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs = 0) 60 v v dgr drain- gate voltage (r gs = 20 k w ) 60 v v gs gate-source voltage 20 v i d drain current (continuous) at tc = 25 o c single operation drain current (continuous) at t c = 100 o c single operation 3 1.9 a a i dm ( ) drain current (pulsed) 12 a p tot total dissipation at t c = 25 o c dual operation total dissipation at t c = 25 o c sinlge operation 2 1.6 w w ( ) pulse width limited by safe operating area type v dss r ds(on) i d STS3DNE60L 60 v < 0.08 w 3 a 1/5
thermal data r thj-amb t j t stg *thermal resistance junction-ambient single operation dual operation maximum operating junction temperature storage temperature 78 62.5 175 -55 to 150 o c/w o c/w o c o c (*) mounted on fr-4 board (t 10 sec) electrical characteristics (t case = 25 o c unless otherwise specified) off symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage i d = 250 m a v gs = 0 60 v i dss zero gate voltage drain current (v gs = 0) v ds = max rating v ds = max rating t c = 125 o c 1 10 m a m a i gss gate-body leakage current (v ds = 0) v gs = 20 v 100 na on ( * ) symbol parameter test conditions min. typ. max. unit v gs(th) gate threshold voltage v ds = v gs i d = 250 m a 1 v r ds(on) static drain-source on resistance v gs = 10 v i d = 1.5 a v gs = 4.5 v i d = 1.5 a 0.065 0.08 0.08 0.1 w w i d(on) on state drain current v ds > i d(on) x r ds(on)max v gs = 10 v 3a dynamic symbol parameter test conditions min. typ. max. unit g fs ( * ) forward transconductance v ds > i d(on) x r ds(on)max i d = 1.5 a 5 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25 v f = 1 mhz v gs = 0 v 815 125 40 pf pf pf STS3DNE60L 2/5
electrical characteristics (continued) switching on symbol parameter test conditions min. typ. max. unit t d(on) t r turn-on delay time rise time v dd = 30 v i d = 10 a r g = 4.7 w v gs = 5 v (resistive load, see fig. 3) 20 45 ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 24 v i d = 3 a v gs = 4.5 v 13.5 8 3.5 18 nc nc nc switching off symbol parameter test conditions min. typ. max. unit t d(off) t f turn-off delay time fall time v dd = 30 v i d = 10 a r g = 4.7 w v gs = 5 v (resistive load, see fig. 3) 40 10 ns ns t r(voff) t f t c off-voltage rise time fall time cross-over time v clamp = 48 v i d = 20 a r g = 4.7 w v gs = 5 v (inductive load, see fig. 5) 10 25 42 ns ns ns source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm ( ) source-drain current source-drain current (pulsed) 3 12 a a v sd ( * ) forward on voltage i sd = 3 a v gs = 0 1.2 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 20 a di/dt = 100 a/ m s v dd = 30 v t j = 150 o c (see test circuit, fig. 5) 65 130 4 ns nc a ( * ) pulsed: pulse duration = 300 m s, duty cycle 1.5 % ( ) pulse width limited by safe operating area STS3DNE60L 3/5
dim. mm inch min. typ. max. min. typ. max. a1.750.068 a1 0.1 0.25 0.003 0.009 a2 1.65 0.064 a3 0.65 0.85 0.025 0.033 b 0.35 0.48 0.013 0.018 b1 0.19 0.25 0.007 0.010 c 0.25 0.5 0.010 0.019 c1 45 (typ.) d 4.8 5.0 0.188 0.196 e 5.8 6.2 0.228 0.244 e1.27 0.050 e3 3.81 0.150 f 3.8 4.0 0.14 0.157 l 0.4 1.27 0.015 0.050 m0.60.023 s 8 (max.) 0016023 so-8 mechanical data STS3DNE60L 4/5
information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this pu blication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectron ics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicr oelectronics. the st logo is a trademark of stmicroelectronics ? 1999 stmicroelectronics C printed in italy C all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - france - germany - italy - japan - korea - malaysia - malta - mexico - morocco - the neth erlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. http://www.st.com . STS3DNE60L 5/5
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